VIT, Chennai, Tamil Nadu

Lab Migration contribution by FOSSEE Club: 

 

FLOSS name (Eg: Scilab, R, DWSIM, etc)

No. of Labs migrated

Year of Migration

Faculty name and contact who was involved in this activity

Link

Scilab

1

2020

Dr. R. Maheswari, Associate Professor, SCOPE, VIT Chennai

maheswari.r@vit.ac.in 

Operating System Lab

Link : https://scilab.in/lab_migration_run/239 

R

1

2020

Dr. R. Parvathi,  Professor, SCOPE, VIT Chennai

parvathi.r@vit.ac.in 

Information Visualization using R

Link : https://r.fossee.in/lab-migration/lab-migration-run/7

R

1

2020

Dr. V. Pattabiraman, Professor, SCOPE, VIT Chennai

pattabiraman.v@vit.ac.in 

Network Data Visualization Using R 

Link: https://r.fossee.in/lab-migration/lab-migration-run/9 

 

  1. Niche Software activity contribution: Please fill in the details of the contribution made to any niche software activities like CFD case studies, eSim circuit simulation, DWSIM or OpenModelica flowsheeting project, etc. in the table given below. If not, please mention not done.

 

FLOSS name (Eg: Scilab, R, DWSIM, etc)

No. of contribution

Year of contribution

Faculty name and contact who was involved in this activity

 

Link

eSim Circuit Simulation Project

72

2021

Dr. Maheswari R

  1.  

Half Adder using NOR Gates

Proposted by : Ms Dikshita Mehta

Guided by :     Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/493

  1.  

Half Adder Using Nand Gates And Sub-Circuit

Proposted by: Mr Akash S

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/491

  1.  

Design of Full Subtractor using Nand gates

Proposted by: Mr. UTUKURI GEYARKA S NIKHILESH

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/488

  1.  

4-Bit Mod-6 Counter Using Jk Flip Flop

Proposted by: Mr Rs Jyothish

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/495

  1.  

4-Bit Even Odd Parity Generator

Proposted by : Ms Vishakha Agarwal

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/496

  1.  

3-Bit Synchronous Down Counter (using Jk Flip Flops)

Proposted by: Mr. Gokul Jayan

Guided by : Dr R. Maheshwari

Link :  https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/489

  1.  

Design Of A 4-Bit Binary Adder Subtractor Circuit In Alu Using Full Adder Subcircuit In Esim

Proposted by: Ms Sai Samyuktha N

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/474

  1.  

4-Bit_asynchronous_down_counter

Proposted by: Mr Tushar Moolchandani

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/482

  1.  
 

1:4 De Multiplexer

Proposted by: Mr Krishna Kumar

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/441

  1.  

Simple Elevator Door Controller For A Three-Story Building Using Esim

Proposted by: Ms Aditi Anil Bodkhe

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/461

  1.  

Full Subtractor Using Nor Gate Only(using 2 Half-Adder As A Subcircuit With Nor Gate Only)

Proposted by: Mr Sumegh Sadashiv Gonugade

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/478

  1.  

Design A Full Adder Using A 3 X 8 Decoder

Proposted by: Mr Siddhant Sharma

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/470

  1.  

3 Bit Synchronous Up Counter Using Jk Flip Flops

Proposted by : Mr Rishi Nair

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/452

  1.  

2 To 4 Decoder (with Enable)

Proposted by: Mr Sam Meshach D

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/450

  1.  

Full Subtractor Using 1x4 De-Multiplexer

Proposted by: Mr Ajith Suresh

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/447

  1.  

Design Of 4 To 2 Priority Encoder Using Sub-Circuit Builder

Proposted by : Mr Akash S

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/445

  1.  

Full Subtractor Circuit Using Subcircuits (2 Half Subtractors)

proposted by : Mr Tarun Elango

Guided by : Dr R. Maheshwari

Link :https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/455

  1.  

Design Of A 4-Bit Bcd To Gray Code Converter Ciruit Using Esim

Proposted by :  Ms Sai Samyuktha N

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/448

  1.  

Bcd To Decimal Code Converter

Proposted by :  Mr Altaf Pathan

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/438

  1.  

3-Bit Asynchronous Up Counter (using Jk Flip Flops)

Proposted by :  Mr Gokul Jayan

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/439

  1.  

2'S Complement Of A 4-Bit Number

Proposted by :  Ms Vishakha Agarwal

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/440

  1.  

Design Of Half Adder Circuit Using Subcircuit Builder In Esim

Proposted by :  Mr S Gopi

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/437

  1.  

Programmable Frequency Divider

Proposted by :  Mr Arjun Bathla

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/427

  1.  

Crc (7, 4) Encoder For Serial Data

Proposted by : Mr Arjun Bathla 

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/425

  1.  

Crc (7, 4) Decoder For Serial Data

Proposted by : Mr Arjun Bathla 

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/426

  1.  

Cyclic Redundancy Check (7, 4) Decoder Circuit

Proposted by :  Mr Arjun Bathla

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/421

  1.  

Transistor Based Three-Phase Sine Wave Generator

Proposted by :  Ms Pravallikaa M

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/424

  1.  

Cyclic Redundancy Check (7, 4) Encoder Circuit

Proposted by  :  Mr Arjun Bathla

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/414

  1.  

Luo Converter

Proposted by :  Ms Krithika B S

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/407

  1.  

3- Bit Even And Odd Parity Generator

Proposted by :  Ms Chirumerla Sri Lahari

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/363

  1.  

Design Of 4-Bit Braun Multiplier Using Kogge-Stone Adder

Proposted by : Mr P Manikandan Nair

Guided by : Dr R. Maheshwari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/359

  1.  

Howland Current Pump Circuit

Proposted by : Mr Naman Girdhar

Guided by : Dr R. Maheshwari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/360

    

  1.  

Analysis Of MOSFET Characteristics

Proposted by : Ms Monica Singh

Guided by : Dr R. Maheshwari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/358

    

  1.  

Asynchronous 4bit Up Counter Using D Flip Flop

Proposted by:  Mr Tushar Moolchandani

Guided by : Dr R. Maheshwari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/514

    

  1.  

8 Bit Asynchronous Up Counter Using Jk Flip Flop

Proposted by :  Mr Tushar Moolchandani

Guided by : Dr R. Maheshwari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/511

    

  1.  

Full Adder Using 3x8 Decoder

Proposted by :  Ms Vaishnavi Shukla

Guided by : Dr R. Maheshwari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/499

    

  1.  

Implementing Sr Flip Flop Using Nand Gates

Proposted by :  Mr Arjun Vishanth

Guided by : Dr R. Maheshwari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/500

    

  1.  

Implementation Of And Gate Logic Using Nand(universal) Gate Logic

Proposted by :  Mr Hari Baskar

Guided by : Dr R. Maheshwari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/505

    

  1.  

Half Adder Using Nor Gates

Proposted by :  Mr Arnab Mondal

Guided by : Dr R. Maheshwari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/502

    

  1.  

3-Bit Asynchronous Down Counter Using D Flip Flops

Proposted by: Mr Rishi Nair

Guided by : Dr R. Maheshwari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/506

    

  1.  

Design Of A Nand Gate Based Decoder With Enable

Proposted by :  Ms Neha Ann Shygen

Guided by : Dr R. Maheshwari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/494

    

  1.  

4 Bit Mod-3 Counter

Proposted by :  Mr Rs Jyothish

Guided by : Dr R. Maheshwari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/503

    

  1.  

Implementation Of Or Gate Using Nor Gate.

Proposted by :  Mr Civanesh C

Guided by : Dr R. Maheshwari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/509]

    

  1.  

Or Gate Using Nand Gate

Proposted by :  Mr Krishna Kumar S

Guided by : Dr R. Maheshwari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/508

    
  1.  

Design of 4 to 1 Multiplexer in eSIM.

Proposted by : Mr . Altaf Pathan

Guided by : Dr.R. Maheswari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/485

  1.  

Full Adder using NAND Gates

Proposted by : Mr . Arnab Monda

Guided by : Dr.R. Maheswari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/490

  1.  

FULL SUBTRACTOR USING 3:8 DECODER 

Proposted by : Mr . Ajith Suresh

Guided by : Dr.R. Maheswari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/484

  1.  

4x1 Multiplexer using 2x1 Multiplexer

Proposted by : Mr . Vinay Karnati

Guided by : Dr.R. Maheswari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/483

  1.  

Design of full Adder using NOR gates

Proposted by : Mr . Abhimanyu Pundir

Guided by : Dr.R. Maheswari 

Link: https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/487

  1.  

Design of 3 x 8 Decoder Using 2 x 4 decoders

Proposted by : Mr.UTUKURI GEYARKA S NIKHILESH

Guided by : Dr.R. Maheswari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/473

  1.  

Half Subtractor Using NAND Gate 

Proposted by : Mr. Sreenath S

Guided by : Dr.R. Maheswari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/480

  1.  

Design of a 4-Bit Binary Combinational Lock using Subcircuit Builder in eSIM

Proposted by : Mr. Navin Kumar M

Guided by : Dr.R. Maheswari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/475

  1.  

4-bit Ripple Counter Using D-flipflops

Proposted by : Mr. Harsh Aryan

Guided by : Dr.R. Maheswari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/476

  1.  

Construction and working of a Full Adder using NgSpice. 

Proposted by : Ms. Vaishnavi Shuukla

Guided by : Dr.R. Maheswari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/472

  1.  

4-Bit Odd-Even Parity Generator and Checker 

Proposted by : Mr. Malay Baldha

Guided by : Dr.R. Maheswari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/459

  1.  

Design Of a 4-Bit Binary to BCD Code Converter Ciruit using Subcircuit Builder in eSIM 

Proposted by : Mr. Gopi. S

Guided by : Dr. R. Maheswari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/463

  1.  

Full Adder using 3 to 8 decoders 

Proposted by : Mr. Vinay Karnati

Guided by : Dr. R. Maheswari

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/462

  1.  

Designing of 3 to 8 line Decoder

Proposted by : Mr. Siddharth Bhuthapuri

Guided by : Dr. R. Maheswari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/469

  1.  

BINARY TO GREY CODE CONVERTER 

Proposted by : Mr. Civanesh C

Guided by : Dr. R. Maheswari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/471

  1.  

4-Bit Asynchronous Up Counter using JK Flip Flop 

Proposted by : Ms. Darshini. R

Guided by : Dr. R. Maheswari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/468

  1.  

Design of Excess-3 to BCD code Conversion 

Proposted by : Mr. Arnab Mondal

Guided by : Dr. R. Maheswari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/464

  1.  

Design of Single-bit Magnitude Comparator

Proposted by : Ms. Preeti Pallavi

Guided by : Dr. R. Maheswari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/466

  1.  

Design of a 4-bit Gray to Binary code converter circuit with Main circuit and Subciruit implementation using eSim

Proposted by : Ms. Sai Samyuktha N

Guided by : Dr. R. Maheswari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/456

  1.  

De Morgan’s Verification Circuit 

Proposted by : Shubhangi Agrawal

Guided by : Dr.R. Maheswari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/465

  1.  

Design of Full subtractor using 4×1 multiplexer as a subcircuit

Proposted by : Mr. Karthik Raj R

Guided by : Dr.R. Maheswari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/460

  1.  

Design of a 4 to 16 Decoder using 3 to 8 Decoder

Proposted by : NEHA ANN SHYGEN

Guided by : Dr.R. Maheswari 

Link: https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/444

  1.  

3-Bit Asynchronous Down Counter 

Proposted by : Dikshita Mehta

Guided by : Dr.R. Maheswari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/458

  1.  

Sequence Detector For The Sequence 1001

Proposted by : Mr Hari Baskar

Guided by : Dr.R. Maheswari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/454

    
  1.  

BCD to Excess 3 Code Conversion 

Proposted by : Mr. Arjun Vishanth

Guided by : Dr.R. Maheswari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/449

    
  1.  

2 - Bit Magnitude Comparator

Proposted by : Mr Sam Meshach D

Guided by : Dr.R. Maheswari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/501

    
  1.  

Design A Full Adder Using A 4:1 Mux

Proposted by : Mr Bhavishya Kumar

Guided by : Dr.R. Maheswari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/510

    
  1.  

Full Wave Rectifier Using Filter

Proposted by : Ms Akanksha Goel

Guided by : Dr.R. Maheswari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/515

    
  1.  

Half Subtractor Using Nor Gates

Proposted by : Ms Darshini R

Guided by : Dr.R. Maheswari 

Link : https://esim.fossee.in/circuit-simulation-project/esim-circuit-simulation-run/516

 

  1. Have your institute encouraged any neighbouring institute to participate in the above activities? Yes / No. If yes, please fill in the details of the contribution made by the neighbouring institutions in the table given below. If not, please mention not done. 

 

Activity name (Eg: Lab Migration, CFD case study, eSim circuit simulation, etc)

FLOSS name (Eg: Scilab, R, DWSIM, etc)

No. of contribution

Year of contribution

Faculty name and contact who was involved in this activity

Link

      
      
      
      
      
      
      

 

FDPs / Workshops where VIT Faculty have acted as a resource person to spread the awareness on FOSSEE and Spoken Tutorial 

S.No

Workshop /event name 

Institute where the event is conducted 

No. of participants 

Date / Duration of the event

Faculty name who was involved in this activity

Participant Category

  1.  

FOSS @ OFTP

VIT

143

22ndJune   2020 /   1 Day

Dr. Maheswari.R

Only VIT

  1.  

Scilab

Government College of Engineering, Tirunelveli

45

2nd July 2020 /1 Day

Dr. Maheswari.R

participants from all neighbouring institutions  

  1.  

Esim –Open Source Electronic Simulator

Government College of Engineering, Tirunelveli

50

06th July 2020/ 1 Day

Dr. Maheswari.R

Participants from all neighbouring institutions  

  1.  

eSim – Open Source Electronic Simulator

Sethu Institute of Technology , Virudhunagar 

120

20th & 21st July 2020/ 2 Days

Dr. Maheswari.R

Participants from all neighbouring institutions  

  1.  

FDP on R for Statistics & Data Analysis

VIT

87

1st to 3rd August  2020/ 3 Days

Dr. Maheswari.R

Across the neighboring institutes and 5 states 

  1.  

Collaborative Learning Through ICT Tools : Hands on Session

Nehru College of Engineering & Research Centre, Kerala

120

2nd & 17th December 2020

Dr. Maheswari.R

Participants from 15 states in India

  1.  

Hands on: Deep Learning Techniques for Analyzing Medical Image using Python- OpenCV

Sri Sai Ram Engineering College

70

30th Jan. 2021/ 1 Day

Dr. Maheswari.R

Participants across institutions from 5 states 

  1.  

Hands on: Deep Learning Techniques for Analyzing Medical Image using Python- OpenCV

Sri Sai Ram Engineering College

80

25th March 2021/ 1 Day

Dr. Maheswari.R

Participants across institutions from 5 states 

  1.  

Design Strategy for Shift Registers using eSim

Bannari Amman Institute Of Technology, Sathyamangalam

70

26th May 2021/ 1 Day

Dr. Maheswari.R

Participants across institutions from 5 states 

  1.  

eSim 2.0

VIT

802

14th to 16th May 2020 /3 Days

Dr. Maheswari.R

Participants from 8 states and 4 countries

  1.  

FDP on  Scilab

Sairam Engineering College 

130

15th May 2020/1 Day

Dr. Maheswari.R

Participants from 10 states 

  1.  

eSim case study presentation

PMMMNMTT – eSim workshop 

 

12th Feb 2020 /1 Day

Dr. Maheswari.R

Participants from all neighbouring institutions  

  1.  

Python Scilab Toolbox Development

VIT

163

14.06.2021 to 15.06.2021 (2 days)

Dr.T.Subbulakshmi

Participants from all neighbouring institutions  

  1.  

C and CPP – Inaugural address 

VIT

79

05.07.2021 to 09.07.2021 (5 days)

Dr.T.Subbulakshmi

Participants from all neighbouring institutions  

  1.  

IoT -  Inaugural AND valedictory address

VIT

98

21.06.2021 to 25.06.2021 (5 days)

Dr.T.Subbulakshmi

Participants from all neighbouring institutions  

  1.  

R - valedictory address

VIT

39

21.06.2021 to 25.06.2021 (5 days)

Dr.T.Subbulakshmi

Participants from all neighbouring institutions  

  1.  

Scilab - Inaugural AND valedictory address & Scilab Toolbox Development

VIT

133

19.05.2021 to 23.05.2021 (5 days)

Dr.T.Subbulakshmi

Participants from all neighbouring institutions  

  1.  

Arduino - valedictory address

VIT

62

09.06.2021 to 10.06.2021 (2 days)

Dr.T.Subbulakshmi

Participants from all neighbouring institutions  

  1.  

Open FOAM - valedictory address

VIT

52

20.05.2021 to 22.05.2021 (3 days)

Dr.T.Subbulakshmi

Participants from all neighbouring institutions  

  1.  

LaTeX - Inaugural AND valedictory address

VIT

395

27.05.2021 to 28.05.2021 (2 days)

Dr.T.Subbulakshmi

Participants from all neighbouring institutions  

  1.  

Linux - Inaugural AND valedictory address & Linux commands for permission management 

VIT

501

10.05.2021 to 14.05.2021 (5 days)

Dr.T.Subbulakshmi

Participants from all neighbouring institutions  

  1.  

Java - valedictory address 

VIT

168

24.05.2021 to 28.05.2021 (5 days)

Dr.T.Subbulakshmi

Participants from all neighbouring institutions  

  1.  

Python, - Python Machine Learning libraries

VIT

449

05.05.2020 to 09.05.2020(5 days)

Dr.T.Subbulakshmi

Participants from all neighbouring institutions  

  1.  

PHPMySql – Software development for academic institutions using PHP MY Sql

VIT

375

11.05.202.0 to 15.05.2020

(5 days)

Dr.T.Subbulakshmi

Participants from all neighbouring institutions  

  1.  

BOSS Linux – Wonders of Linux

VIT

383

14.05.2020/1 day

Dr.T.Subbulakshmi

Participants from all neighbouring institutions  

  1.  

Online Faculty Training Program

VIT

 

2020

Dr.T.Subbulakshmi

Only VIT 

  1.  

Online Faculty Induction Program

VIT

 

2021

Dr.T.Subbulakshmi

Only VIT 

  1.  

AICTE-ISTE Induction/refresher program on an effective pedagogy practice – KLN College of Engineering,

Tamilnadu

 

60

23/04/2021

Dr.T.Subbulakshmi

participants from all neighbouring institutions  

  1.  

AICTE-ISTE Induction/refresher program on an effective pedagogy practice – KLN College of Engineering,

Tamilnadu

 

60

14/05/2021

Dr.T.Subbulakshmi

participants from all neighbouring institutions  

  1.  

AICTE-ISTE Induction/refresher program on an effective pedagogy practice – KLN College of Engineering,

Tamilnadu

 

60

05/03/2021

Dr.T.Subbulakshmi

participants from all neighbouring institutions  

  1.  

FOSS Tools of Engineering Laboratories KLN

 

100

 

Dr.T.Subbulakshmi

participants from all neighbouring institutions  

  1.  

STTP on Utilizing AI and Tools in real time problems BITS

 

50

21/09/2020

Dr.T.Subbulakshmi

participants from all neighbouring institutions  

 

  1. The number of neighboring or other institutes invited for the Spoken tutorial-based workshop on any of the FOSSEE supported software? Please fill in the details of the workshop conducted in the table given below. If not, please mention not done. 

 

FDPs / Workshops conducted by VIT Chennai from May 2020 to till date. 

 

Sl.No

FLOSS name (Eg: Scilab, R, DWSIM, etc)

Workshop date/duration 

No. Workshop Registrations 

No. Workshop participants

Faculty name and contact who was involved in this activity

Link (if any)

  1.  

Python 

05-05-2020 to 09-05-2020 

(5 days)

710

449

Dr. V.M. Nisha

https://sites.google.com/site/glugvitcc/onlinefdps_vit_iitb 

  1.  

PHP and MySQL

11-05-2-2020 to 15-05-2020(5 days)

819

375

Dr. N. Hema

https://sites.google.com/site/glugvitcc/onlinefdps_vit_iitb 

  1.  

JAVA

15-05-2-2020 to 16-05-2020 (2 days)

285

205

Dr. S. Shridevi

https://sites.google.com/site/glugvitcc/onlinefdps_vit_iitb 

  1.  

Ruby 

11-05-2020 to 12-05-2020 (2 days)

458

276

Dr. S. Rajarajeswari

https://sites.google.com/site/glugvitcc/onlinefdps_vit_iitb 

  1.  

Advanced CPP

13-05-2020 to 14-05-2020 

(2 days)

98

58

Dr. V. Muthumanikandan

https://sites.google.com/site/glugvitcc/onlinefdps_vit_iitb 

  1.  

BOSS Linux

14-05-2-2020 (one day)

546

383

Dr. M. Prasad

https://sites.google.com/site/glugvitcc/onlinefdps_vit_iitb 

  1.  

MOODLE

13-05-2020 to 15-05-2020 (3 days)

783

582

Dr. M. Priyaadarshini

https://sites.google.com/site/glugvitcc/onlinefdps_vit_iitb 

  1.  

eSim

14-05-2020 to 16-05-2020 (3 days)

780

460

Dr. Maheswari R

https://sites.google.com/site/glugvitcc/onlinefdps_vit_iitb 

  1.  

PostgreSQL

09-05-2020 to 10-05-2020 (2 days)

219

145

Dr. S. Sajidha

https://sites.google.com/site/glugvitcc/onlinefdps_vit_iitb 

  1.  

R Programming

14-05-2020 to 15-05-2020 (2 days)

170

94

Dr. R. Bhargavi

https://sites.google.com/site/glugvitcc/onlinefdps_vit_iitb 

  1.  

Android

05.06.2021 & 06.06.2021 (2 days)

116

71

Dr. Shola Usha Rani

Dr. R. Gayathri

https://sites.google.com/view/onlineworkshopsvit/home?authuser=0 

  1.  

Arduino

09.06.2021 to 10.06.2021 (2 days)

128

62

Dr. Chanthini,

Dr. Gayathri Sivakumar

https://sites.google.com/view/onlineworkshopsvit/home?authuser=0 

  1.  

Java

24.05.2021 to 28.05.2021 (5 days)

403

168

Dr. R. Radha, 

Dr. R. Jayanthi

https://sites.google.com/view/onlineworkshopsvit/home?authuser=0

  1.  

LaTex

27.05.2021 to 28.05.2021 (2 days)

802

395

Dr. Parthiban

Dr. Manivannan

https://sites.google.com/view/onlineworkshopsvit/home?authuser=0

  1.  

Linux

10.05.2021 to 14.05.2021 (5 days)

698

501

Dr. Sakthivel

https://sites.google.com/view/onlineworkshopsvit/home?authuser=0 

  1.  

OpenFoam

20.05.2021 to 22.05.2021 (3 days)

250

28

Dr. Manimaran

https://sites.google.com/view/onlineworkshopsvit/home?authuser=0 

  1.  

Python_ML

14.06.2021 to 18.06.2021 (5 days)

254

242

Dr. Shoba, 

Dr. Braveen, 

Dr. Suganya, 

Dr. Premalatha

https://sites.google.com/view/onlineworkshopsvit/home?authuser=0 

  1.  

R

21.06.2021 to 25.06.2021 (5 days)

105

43

Dr. Rajalakshmi, 

Dr. Sathiyanarayan

https://sites.google.com/view/onlineworkshopsvit/home?authuser=0 

  1.  

Ruby

07.06.2021 to 08.06.2021 (2 days)

42

25

Dr. R. Rajarajeswari

https://sites.google.com/view/onlineworkshopsvit/home?authuser=0 

  1.  

Scilab Intro

19.05.2021 to 23.05.2021 (5 days)

133

74

Dr. Richards Joe Stanislaus, 

Dr. A. Sasithradevi, Dr. Ranjeet Kumar, 

Dr. Ashish Kumar

https://sites.google.com/view/onlineworkshopsvit/home?authuser=0 

  1.  

C and CPP

05.07.2021 to 09.07.2021 (5 days)

81

79

Dr.S.Geetha , Dr.S.Asha, Dr.R.Jothi,

Dr.A.Bhuvaneswari

https://sites.google.com/view/onlineworkshopsvit/home?authuser=0 

  1.  

Prehackathon Scilab toolbox development workshop for VIT Students

26.05.2020

50

40

Dr. T. Subbulakshmi & Dr. R. Maheswari

 
  1.  

Online Faculty Development Program

15.06.2020

20

20

Dr. T. Subbulakshmi

 
  1.  

Online Faculty Induction Program

16.06.2021

143

130

Dr. T. Subbulakshmi

 
 

Total number of participants

8043

4865

(60 % of registrations are completed)

 

 

  1. Has your institute interfaced any Hardware with software? Please mention the details if any. Also, provide relevant links. 

 

We have submitted the following experiments on Scilab Arduino and waiting for a response from the FOSSEE FLOSS Arduino team. 

 

1) Constant frequency and pulses to Zcos(arduino_scope)

2) Constant frequency and pulses to Zcos and digital write(arduino UNO)

3) adding 0.5 to 2nd experiment(to obtain the constant wave ranging in between 0 and 1)

4) analog read and write to zcos and arduino

 

  1. Has your institute provided a cloud version for any of the FLOSS? You can refer to point no. 6 of the EOI to answer this question?

 

  1. https://scipy.in/2020#speakers 

  • VPropel  is Used in four campuses of VIT say Vellore, Chennai, AP, and Bhopal and volunteered to the IIT Bombay workshops  

 

  1. The number of Spoken Tutorials created on new FLOSS or advanced series for existing FLOSS. Please fill in the details of the workshop in the table given below. If not, please mention not done.

 

FLOSS name (Eg: Scilab, R, DWSIM, etc)

Name of Spoken tutorial created

Contributor name/(s)

Year of contribution

Faculty name and contact who was involved in this activity

Link of the published tutorial (if any)

Scilab Toolbox

Developing Scilab Toolbox for calling Python and its function

Dr. T. Subbulakshmi

2020

Dr. T. Subbulakshmi

Subbulakshmi.t@vit.ac.in 

https://spoken-tutorial.org/watch/Scilab/Developing+Scilab+Toolbox+for+calling+Python+

and+its+functions/English/

 

  1. Has your institute contributed to the development of FLOSS like creating toolboxes in Scilab, fixing bugs, etc? 

 

Yes we have created the following toolboxes 

 

Scilab Python : ATOMS link  : https://atoms.scilab.org/toolboxes/scithon/1.0.1

Scilab R : Atoms Link : https://atoms.scilab.org/toolboxes/SciR 

 

  1. Any other contributions made by your FOSSEE club? 

 

Contribution 1 : Internship from VIT FOSSEE Club 

 

VIT FOSSEE Club Internships to VIT Chennai Students during June 2020  

 

Sl.No

Student Name

Guide Name 

Software Used 

  1.  

Jishnu

Dr. Subbulakshmi T

Scilab - Python

  1.  

Dheeksha

Dr. Subbulakshmi T

Scilab - Python

  1.  

Aakash Ezhilan

Dr. Subbulakshmi T

Scilab - Python

  1.  

Mahesh

Dr. Subbulakshmi T

Scilab - Python

  1.  

Adrian Andrew

Dr. Subbulakshmi T

Scilab - Python

  1.  

Adityan Sunil kumar

Dr. Subbulakshmi T

Scilab - Python

  1.  

Tarun A H

Dr. R. Mohana 

Scilab – R 

  1.  

Venkat Ragavan S

Dr. R. Mohana 

Scilab – R 

  1.  

Akash Manish Lad

Dr. R. Mohana 

Scilab – R 

  1.  

Garima Dave

Dr. R. Mohana 

Scilab – R 

  1.  

Aravind Krishna R

Dr. R. Maheswari

Scilab - OpenMP

  1.  

Surya Prasad S

Dr. R. Maheswari

Scilab - OpenMP

  1.  

Tharun Bhargav A

Dr. R. Maheswari

Scilab - OpenMP

  1.  

Yeshwanth R

Dr. R. Maheswari

Scilab - OpenMP

 

VIT FOSSEE Club Internships to VIT Chennai Students during December 2020 

 

Sl.No

Student Name

Guide Name

Software used 

  1.  

S Vighnesh

Dr. Subbulakshmi T

Scilab

  1.  

Varikuti Abinash Reddy

  1.  

Chandra Deep Rathan K

  1.  

Preethi Chandirasekeran

Dr. Sweetlin Hemalatha 

R

  1.  

Ayanabha Jana

  1.  

P Manikandan Nair

Dr. Maheswari R

eSim

  1.  

N. Karthikeyakumar

  1.  

Chirumerla Sri Lahari

  1.  

Monica Singh

  1.  

Naman Girdhar

  1.  

Pranhav V 

Dr. Anuradha J

Python 

 

VIT FOSSEE Club Internships to VIT Chennai Students during July 2020  (Yet to be finalized) 

 

 

Sl.No.

Name of the Student

Guide Name

S/W Used

1

Karthick Srivatsa R

Dr Subhashini N

eSim

2

Prarthana Prasanna Kumar

3

Tahanvi Yadav

4

Ashita Banger

5

Jananya Sivakumar

Dr.P.Subbulakshmi

R

6

Mohit Singh Bisht

7

Shivansh Jain

8

Priyanshu

9

Shaunak Deshpande

Dr. Ramesh Ragala

R

10

Tanisha Mandal

11

Jeevesh Singh

Prof. Dr. Parvathi R

QGIS

12

Krithika B S

Dr. R Maheswari

eSim

13

Arjun Bathla

14

Achyut Agrawal

15

Parth Birthare

Subbulakshmi T

Scilab

16

LEKHA SHIVANI A

17

Anto Joy

18

 

AYUSHI JAIN

19

Devansh Kumar

 

Contribution 2 : Final Year Project Internship on FOSSEE eSim Circuit Simulation from Jan., 2020 to March 2020

 

Student Name

Programme

External Mentor

Ashutosh Jha

Final Year B.Tech EEE

Dr. Kannan Moudgalya, Professor, IIT Bombay

 

Contribution 3 

 

VIT Chennai have served as organizer for

Scilab Toolbox Development Hackathon  held during June 2020 

https://scilab.in/hackathon/ 

Pic : Webpage screenshot with VIT as Organizer for the Scilab Toolbox Development Hackathon 

Contribution 4 : 

 

VIT Chennai, served as organizer / contributor 

for the 

‘R Advanced One Week Workshop ending on 21 November 2020 and R Beginner Workshop scheduled on 28th November 2020’ – organized by FOSSEE, IITBombay, Spoken Tutorial under the  Pandit Madan Mohan Malaviya National Mission on Teachers and Teaching (PMMMNMTT)

 

Mode of workshop : Online 

Link for R Basic workshop : https://drive.google.com/drive/folders/1RVL17cp_PJvkeysQSaWKH6V8qDeRigx9?usp=sharing 

Link for R Advanced workshop : https://drive.google.com/drive/folders/1zUC8DDR_puXz2dQVh5_-lQPk_3YjSx-P?usp=sharing 

Faculty Details 

 

    

 

    

 

     

 

Contribution 5 : 

 

VIT Chennai faculty served as guest speaker 

for the following workshops organized by 

FOSSEE, IITBombay, Spoken Tutorial under the  Pandit Madan Mohan Malaviya National Mission on Teachers and Teaching (PMMMNMTT)

 

1. R  workshop  held on 29-01-2021 & 30-01-2021 

 

Dr. T. Subbulakshmi, Professor, SCOPE, VIT Chennai – Title : Case study presentation of R usage in Indian universities 

Dr. Sweetlin Hemalatha, Associate Professor, SCOPE, VIT Chennai – Title : R Lab migration development

Link for the workshop videos :  https://youtube.com/playlist?list=PLBPlmyCeNLdVwcCMsg7T-x_gyTmm_GEZW 

Link for our talk : https://youtu.be/o5j_UVHnjqs 

 

    

 

 

 

Contribution 6 

 

2. Scilab workshop held on 27-04-2021 

 

Workshop link : https://youtube.com/playlist?list=PLBPlmyCeNLdWu8MzzSUIppIiaF8LhpEpK 

 

Guest Speakers from VIT Chennai 

 

Talk 1 : 

Dr. T. Subbulakshmi, Professor, SCOPE, VIT Chennai – Title : Migration to Scilab 

https://youtu.be/q_SAYVgDxWs 

 

Talk 2 : 

 

Scilab Python Student Development Team

 

https://youtu.be/TSrLOFDPPmk

 

    

 

 

Contribution 7 

 

3. eSim workshop held on 22-03-2021

Guest Speakers from VIT Chennai : Dr. R. Maheswari, Associate Professor, SCOPE, VIT Chennai 

Link for workshop : https://youtube.com/playlist?list=PLBPlmyCeNLdVe3oAFMPELMqn6SsqYHqCB 

Link for VIT talk : https://youtu.be/4jZQCL3-1Gc 

 

 

Contribution 8 

 

Scipy India 2020

 

FOSSEE - International Conference Presentation 

 

Dr. Janakimeena, Dr. Sweetlin Hemalatha, “Online Programming Portal with Code Plagiarism Checker using Python Packages", Dec 18th, 2020. SciPy India 2020, IIT Bombay